Shelby Hall Graduate Research Forum Posters
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Description
In memory design, silicon area and power savings have always been a major concern as it directly contributes to performance improvement and cost reduction. The chip area is defined by the area occupied by each memory cell, while the cell area greatly depends on the size of the transistors. In custom design of memory cells, the transistor size is determined based on static noise margin (SNM) which defines the maximum tolerable noise for a cell without any changes in its operational state. This research introduces a hardware based custom 4-transitor (4T) static random-access memory (SRAM) design that supports differential privacy in Internet of Things (IoT) devices as well as reduces 61.92% silicon area and 38% power compared to the traditional 6-transistor (6T) SRAM. Combining 6T and 4T cells together and applying voltage level variations inside the array introduces a high-quality differential privacy mechanism. In addition to that, the 4T cells show a great potential to minimize silicon area compared to 6T cells as these cells do not include the pull-up devices. Moreover, a mirror-based highly compact layout design of the 4T SRAM is presented where the adjacent cells in the array can share some specific elements both vertically and horizontally. This mirrored cell structure greatly helps to reduce the area occupied by each 4T cell as well as the overall silicon area. For physical design, implementation, verification and analysis, a 130nm CMOS technology from SkyWater and EDA tools provided by Efabless (such as NGSPICE, Magic, and XSchem) are used.
Publication Date
3-2025
Department
Systems Engineering
City
Mobile
Disciplines
Information Security | OS and Networks | Other Operations Research, Systems Engineering and Industrial Engineering | Programming Languages and Compilers | Software Engineering | Systems Architecture | Systems Engineering
Recommended Citation
Haq, Safa; Mooney, Kyle; Renteria-Pinon, Mario; Das, Hritom; Liu, Jianqing; and Gong, Na, "Low-Cost Memory Design for Data Privacy" (2025). Shelby Hall Graduate Research Forum Posters. 28.
https://jagworks.southalabama.edu/southalabama-shgrf-posters/28
Included in
Information Security Commons, OS and Networks Commons, Other Operations Research, Systems Engineering and Industrial Engineering Commons, Programming Languages and Compilers Commons, Software Engineering Commons, Systems Architecture Commons, Systems Engineering Commons