Honors Theses
Date of Award
8-2025
Document Type
Undergraduate Thesis
Degree Name
BS
Department
Electrical and Computer Engineering
Faculty Mentor
Samuel Russ
Advisor(s)
Edmund Spencer, Mohamed Shaban
Abstract
This project presents the development of a high-performance, cost-effective, and powerefficient pipelined architecture designed to execute 10,000 Fast Fourier Transforms (FFTs) per second on an Efinix Trion T120 FPGA. Each FFT processes 4096 signed 13-bit elements, facilitating real-time data analysis for a Time-Domain Impedance Probe (TDIP) operating at a maximum data rate of 490 Mbit/s. The algorithm utilizes the built-in multipliers and dual-port memory cells of the FPGA to optimize data storage, transfer, and processing. It achieves this high performance while only using approximately 4% of the Look-Up Tables (LUTs), 7% of the integrated RAM cells, and 15% of the multipliers available in the FPGA. The Verilog implementation successfully performs one FFT in 6216 clock cycles with a maximum clock rate of 58.8 MHz, permitting 9459 FFTs/second/ module.
Recommended Citation
Cashwell, Luke, "Development of a High-Performance, Cost-Effective Architecture for Real-Time Fourier Transform Analysis on an Efinix Trion FPGA" (2025). Honors Theses. 120.
https://jagworks.southalabama.edu/honors_college_theses/120