Shelby Hall Graduate Research Forum Posters

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Description

As the complexity in memory chip architecture is increasing, it is essential to have efficient, reliable and adaptive test methodology to ensure memory’s performance, functionality and error detection. This research work presents a testing and verification method which integrates FPGA (Field Programmable Gate Array) and API (Application Programming Interfaces) to ensure automation and scalability in evaluating memory chip performance. The proposed methodology uses FPGA-based test environments to develop predefined and controlled test pattern, simulate real time memory operations and capture responses under different conditions. The APIs facilitate real-time and uninterrupted data communication between host side and FPGA test platform. API plays the key role to automate the testing procedure with diverse conditions by sending data from host side to FPGA and receiving data from FPGA testbed to host side. By integrating automation, real-time fault detection and modifying test algorithms, this procedure improves testing speed and efficiency compared to conventional testing methodologies. This study includes an analysis of FPGA configuration, automation through API and performance comparison, which reflects lower test time and precise fault detection. This result demonstrates how this testing framework offers a cost-effective, scalable and adaptable solution for modern memory chip validation.

Publication Date

3-2025

Department

Systems Engineering

City

Mobile

Disciplines

Computer and Systems Architecture | Operations Research, Systems Engineering and Industrial Engineering | Other Operations Research, Systems Engineering and Industrial Engineering

API and FPGA-Based Methodology for Memory Chip Testing

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